Yes correct.
If one knows witch parameters to use for feadis wrt.exe there is no obvious reason way one should use the wrtjp.5.1.
There are many improvements made to wrtjp.5.1 but in the end, less is sometimes more.
(Feadi never published the source of his changes to HairyDairyMaidy 4.8 Version. My adaptions ware made on base of HairyDairyMaidy Version 4.8 and the Application Notes published by Xilinx
http://www.xilinx.com/support/documentation/application_notes/xapp058.pdf
http://www.xilinx.com/support/documentation/application_notes/xapp424.pdf
See also:
ftp://ftp.xilinx.com/pub/swhelp/cpld/eisp_pc.zip)
If one has a print without knowing the parameters wrtjp.5.1 will usually identify and readout the chips found.
A new parameter (/check) was added so one can double check reading and check on ever rif the written byte was written correctly. Only in use if PrAcc read writes are used. DMA read write don't work on AVM routers anyway. This option is not set by default because it makes reading and writing much slower.
Cabling should be much less critical as it is with wrt.exe or any older HaryDaryMad tool.
Sometimes older tools just exit with a segmentation fault, because the PrAcc read or write routine had no checking for addressing overflow. Or some routine just did a endless loop without timeout if wrong information was read from the buss.
There may still be space to improve or enhance this software.
EDIT2:
Reading 0x1000 Bytes takes 11 seconds and with wrt.exe 15 seconds.
Writing 0x1000 Bytes takes 80 seconds and with wrt.exe 104 seconds.
So it is actually a bit faster as the older reading or writing routines.
Linux Version is slower as the Windows Version, if low level port routines would be in assembler this could be as fast as windows version.
Reading 0x1000 Bytes takes 16 seconds.
Writing 0x1000 Bytes takes 115 seconds.
And don't forget that the tool has built in debugging (Option /debug2) down to every single bit read or written to the EJTAG bus. This is not important if everything is working but if one wants to learn how EJTAG is functioning or find out what is not running proper then one can do debugging with some background information on this subject.
So for persons who would like to understand how JTAG is working it would be a very nice tool.
Option /test is very good suitable to do single stepping on the JTAG bass as well.
And it is usable to check the wiring in combination with a logic-tester or multimeter or Oscilloscope.
Test option /test clocking can be used to find the Chain TDO wire on the print by searching for hot spots while looking for a clock signal.
, but I see that many of you understand and speak english, not me deutsch. Btw, I am hungarian.
